1. Field of the Invention
The present invention relates generally to semiconductor memory devices and manufacturing methods thereof, and more specifically, to a semiconductor memory device allowing writing of data at a time to a plurality of memory cells connected to one word line and a operating method thereof.
2. Description of the Prior Art
Conventionally, there is known a method of writing same data to all of memory cells connected to one word line at a time for achieving high speed accessing to a semiconductor memory device (hereinafter the method will be referred to as flash write).
FIG. 7 is a block diagram showing a conventional dynamic semiconductor memory device. Referring to FIG. 7, the semiconductor memory device includes memory cells 1 arranged in a matrix, word lines 2 provided correspondingly to the rows of the matrix, and bit lines 3A on the side of BL and bit lines 3B on the side of /BL provided alternately and correspondingly to the columns of the matrix. The bit lines 3A and 3B are provided adjacent to each other in pairs. The memory cells 1 are each provided at a crossing point of a word line 2 and one of the bit lines 3A on the BL side and the bit lines 3B on the /BL side which are alternately arranged.
The semiconductor memory device includes external terminals 6A to 6G. Row and column address signals for a memory cell 1 to and from which data is input and output are input at the external terminal 6A. The external terminals 6B and 6C are provided with a /RAS (Row Address Strobe) signal and a /CAS (Column Address Strobe) signal, respectively which are clock signals for internally in taking the row and column address signals. The external terminals 6D and 6E each output and input a data signal. A /WE signal which is a clock signal for intaking an externally applied data signal inside is input at the external terminal 6F. The external terminal 6G is provided with a signal DSF (Data-in Special Flag) for designating a flash write mode.
The semiconductor memory device shown in FIG. 7 further includes, as a peripheral circuit for the memory cell array, an address buffer 7, an RAS buffer 8, a CAS buffer 9, a row decoder 10, a column decoder 11, a data input/output line 12, an input/output gate 13, a sense amplifier 14, a preamplifier 15, a main amplifier 16, an input data buffer 17, a WE buffer 18, a DSF buffer 21, and a flash write signal generation circuit 22. The address buffer 7 changes the level of a signal input to the external terminal 6A. The RAS buffer 8 changes the level of the /RAS signal applied to the external terminal 6B. The CAS buffer 9 changes the level of the /CAS signal applied to the external terminal 6C. The row decoder 10 is provided between the address buffer 7 and the word lines 2 and selects a designated word line 2 in response to a row address signal from the address buffer 7. The column decoder 11 is provided between the address buffer 7 and the bit lines 3A, 3B and selects a designated bit line pair 3A, 3B in response to a column address signal from the address buffer 7. The data input/output line 12 input/outputs data to/from a memory cell 1. The input/output gate 13 is provided between the bit lines 3A, 3B and the input/output line 12 and has its one source/drain electrode connected to a bit line, its the other source/drain electrode connected to the input/output line 12, and its gate electrode connected to the column decoder 11. The sense amplifier 14 amplifies the potential difference between the bit lines 3A and 3B. The preamplifier 15 amplifies a data signal with a small potential difference appearing on the input/output line. The main amplifier 16 amplifies a data signal from the preamplifier 15 for output. The input/output data buffer 17 changes the level of data input to the external terminal 6E. The WE buffer 18 changes the level of an external write signal /WE applied to the external terminal 6F. The DSF buffer 21 changes the level of a flash write mode designation signal DSF applied to the external terminal 6G. The flash write signal generation circuit 22 generates a flash write signal FW in response to a signal output from the DSF buffer 21 and a row address strobe signal output from the RAS buffer 8.
FIG. 8 is a circuit diagram showing a flash write signal generation circuit 22 shown in FIG. 7. FIG. 9 is a timing chart for use in illustration of the operation of the flash write signal generation circuit 22 shown in FIG. 8.
Referring to FIG. 8, the flash write signal generation circuit 22 includes a logic gate 22a, a clocked inverter 22b, and inverters 22c-22f. The logic gate 22a is an OR gate in positive logic. The clocked inverter 22b inverts the output of logic gate 22a in response to a /RAS signal and an output signal from the inverter 22c. The inverters 22d and 22e constitute a latch circuit and hold the output level of the clocked inverter 22b. The inverter 22f inverts the output level of inverter 22d, and the resultant inverted output signal is output to a column decoder 11 as a flash write signal FW.
Now, referring to FIG. 9, the operation of the flash write signal generation circuit 22 shown in FIG. 8 will be described. At the time of usual operation, the DSF signal is at an L level, and the flash write signal FW is maintained at the level since the clocked inverter 22b does not invert an output signal if the /RAS signal rises.
Meanwhile, in a flash writing operation, the DSF signal is temporarily pulled to an H level, and the clocked inverter 22 detects the DSF signal (H level) in the falling timing of the /RAS signal and applies the H level to the inverters 22d and 22e. The inverters 22d and 22e latch the output of clocked inverter 22b (H level). The output of inverter 22d is inverted at the inverter 22f, and thus inverted signal is applied to the column decoder 11 as the flash write signal FW.
FIG. 10 is a flow chart for use in illustration of a usual operation of a semiconductor memory device as shown in FIG. 7, and FIG. 11 is a timing chart in a usual operation. FIG. 12 is a flow chart for use in illustration of a flash writing operation, and FIG. 13 is a timing chart in a flash writing operation.
A description of an operation of the semiconductor memory device shown in FIG. 7 follows. When a usual reading operation is conducted as shown in FIG. 10 and FIG. 11, (1) a row address signal is input to the external terminal 6A. (2) The /RAS signal from the external terminal 6B activates the row decoder 10, and the row address signal is decoded. Thus, a designated row is selected. If the memory cell 1 is divided into a plurality of blocks, one word line 2 in a unit block is selected. (3) The sense amplifier 14 is operated to amplify the potential difference between the bit line 3A and 3B. (4) A column address signal is taken in by activating the column decoder 11 by the /CAS signal, a pair of bit lines 3A and 3B corresponding to the taken in column address signal is selected, thereby turning on the input/output gate 13, and the potential difference between the bit lines 3A and 3B is transmitted on the input/output line 12. (5) The above-stated potential difference is amplified by the preamplifier 15, and the amplified potential difference is transferred to the main amplifier 16 and output as a data signal to the external terminal 6D.
When a usual writing operation is conducted, a word line corresponding to a row address signal and a bit line corresponding to a column address signal are selected as in the same manner as the above-stated reading operation, and the sense amplifier 14 is activated. A write data signal from the external terminal 6E is taken inside by the /WE signal from the external terminal 6F and transmitted on the input/output line 12 from the input data buffer 17. Thus, the potential difference between the bit line 3A and 3B amplified by the sense amplifier 14 are forced to be the potential difference transmitted on the input/output line 12, and the potential is stored in a selected memory cell.
Other than the usual reading and writing operations, the semiconductor memory device shown in FIG. 7 conducts special operations such as a flash write operation by which the contents of all the memory cells 1 connected to one word line 2 are replaced with the same data in one cycle as shown in FIG. 12 and FIG. 13. In operation at the time of flash write, (1) a row address signal is input to the external terminal 6A, while the DSF signal is input to the external terminal 6G. (2) The row decoder 10 is activated by the /RAS signal from the external terminal 6A, and the row address signal is decoded by the row decoder 10. Thus, one of the word lines 2 in the unit block is selected. (3) The flash write signal generation circuit 22 generates the flash write signal FW in response to the /RAS signal and the DSF signal and provides the generated flash write signal FW to the column decoder 11. This activates the column decoder 11, and all the bit lines 3A and 3B in the unit block are connected en bloc to the input/output line 12. (4) A data signal registered in an internal register which is not shown, or a data signal input from the external terminal 6E to the input data buffer 17 is transmitted on the input/output line 12. (5) The sense amplifier 14 is operated to amplify the potential difference between the bit lines 3A and 3B, and the amplified potential difference is written into all the memory cells 1 connected to the above-stated one word line 2 as data.
As stated above, the flash write operation is very much different from the usual mode in its logical operation procedure. Especially when a data signal is written in bit lines 3A and 3B from the input/output line 12, only the pair of bit lines 3A and 3B are connected to the output line 12 in the usual mode, but all of the bit lines 3A and 3B in a unit block are connected at the time of the flash write operation, thus increasing load capacity. This is a reason for low operating speed and large power consumption.
As illustrated in FIG. 13, since the sense amplifier 14 attains an active state (100 nsec) and a precharge state (40 nsec) in the same cycle as the /RAS signal, 140 nsec is necessary for flash writing operation for one row.
In order to solve the problem of large power consumption, the use of a memory cell for flash write for each of the memory cells as shown in FIG. 14 has been considered (see Japanese Patent Laying-Open No. 2-189790). The memory cell shown in FIG. 14 includes a second word line 19 provided in parallel to each word line 2, a second bit line 20 provided in parallel to each bit line 3A, a switching transistor 21 provided at the crossing point of the second word line 19 and the second bit line 20, and a switch circuit 22 for applying fixed data (power supply potential or ground potential) to the second bit line 20.
In the memory cell shown in FIG. 14, the second word line 19 activates the switching transistor 21, and fixed data is applied to the second bit line 20. Thus, the flash write and the initialize mode can be executed without utilizing a column decoder.
In the memory cell shown in FIG. 14, however, the area of the memory cell array is increased by the provision of a second word line 19, a second bit line 20 and a switching transistor 21 for each memory cell. This is therefore a room for improvements.